The semiconductor industry has been advanced in an ever brisk pace, recently. In order to achieve high performance integrated circuits or high package density of a wafer, the sizes of semiconductor devices have become smialler and smaller than before in the field of Ultra Large Scale Integrated (ULSI) technologies. Integrated circuits includes more than millions devices in a specific area of a wafer and electrically connecting structure for connecting these devices to perform desired function. One of the typical devices is mental oxide semiconductor field effect transistor (MOSFET). The MOSFET has been widely, traditionally applied in the semiconductor technologies. As the trend of the integrated circuits, the fabrication of the MOSFET also meets various issues to fabricate them. The typical issue that relates to hot carriers injection is overcome by the development of lightly doped drain (LDD) structure.
The thin film silicon on insulator (SOI) structure is interest due to potentially alleviated short channel effects. Further the requirement of the devices towards high driving capability. For deep sub-micron meter MOS devices, the SOI (silicon on insulator) is an ideal structure for forming the MOS devices. At present the thin film on the SOI structure plays an important role in the evolution in the semiconductor technologies due to the requirement of the low operation power and power consumption. Further, the fully-depleted (FD) SOI MOS offers a higher driving capability, reduced parasitic capacitance and reduced short channel effects as compared to the bulk or partially (PD) SOI MOS. One device that has been proposed for ultra-low voltage operation is a configuration of a PD SOI structure. An article relating to the SOI is "Thin Film Silicon on Insulator: An Enabling Technology", Michael Alles, et al., Semiconductor international, p. 67, 1997. One of the methods to form the SOI structure is called SIMOX (separation by implantation of oxygen). The method involves the implantation of oxygen ions into a substrate, then the following step is performed by a high temperature anneal. Wafer bonding is another primary means of low cost for forming the SOI structure. Two wafers respectively have oxide on the surfaces. The two wafer are bounded together by joining at room temperature, followed by an anneal to strengthen the bond.
However, the high series source and drain (S/D) resistance of the thin FD SOI transistors will limit the device performance. Su has proposed a method to reduce the series resistance in "Optimization of Series Resistance in Sub-0.2 .mu.m SOI MOSFET'S", L. K. Su et al., IEEE, Electron Device Lett., vol. EDL-15, P. 145, 1994. One of the solutions is the use of silicide to reduce the S/D sheet resistance. Su used the titanium/cobalt silicidation to overcome the issue. Also, it is difficult to define the gate length to below 0.1 .mu.m due to the limit of current optical lithography. Please refer to "Short-Channel-Effect-Suppressed Sub-0.1-.mu.m Grooved-Gate MOSFET'S with W Gate", S. Kimura et al., IEEE Trans. Electron Device Lett., vol. ED-42, P. 94, 1995. In the paper, Kimura disclosed a grooved-gate Si MOS with tungsten gates to suppress the short channel effect.